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TELEFUNKEN Semiconductors
U6225B
2.9 GHz PLL for SAT TV Receiver with Universal Bus
Description
The U6225B is a single chip PLL for SAT-TV tuners. It contains on one chip all functions required for PLL control of a VCO. This IC also contains a high frequency prescaler and can handle frequencies up to 2.9 GHz. The U6225B has a fixed reference divider of 512, while the U6223B has a programmable 256/ 512/ 1024 reference divider.
Features
D 2.9 GHz divide-by-16 prescaler integrated D Universal bus:
I2C-bus or 3-wire-bus I2C-bus software compatible to U6204B 3-wire-bus software compatible to U6358B (19 bit)
Benefits
D Only one device for 3-wire bus applications and I2Cbus applications necessary (universal bus)
D High input frequency of 2.9 GHz applicable for all
TV-satellites
D I2C-bus mode:
5 switching outputs (open collector) 4 addresses selectable at pin 10 for multituner application
D 3-wire-bus mode:
4 switching outputs (open collector) Locksignal output (open collector)
D Low power consumption (typical 5 V / 23 mA) D Electrostatic protection according to MIL-STD 883
Ordering Information
Extended Type Number U6225B-FPG3 Package SO16 Remarks Taped and reeled
Rev. A1: 25.10.1995
1 (12)
U6225B
Block Diagram
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Lock SW4 SW6 SW7 SW5 SW1 11 9 8 76 AS ENA 10 SCL 5 SDA 4 T1 5 BIT LATCH SWITCHING OUTPUTS
UNIVERSAL BUS CONTROL
7 BIT LATCH
8 BIT LATCH
4 BIT LATCH
GATE
15 BIT LATCH
OS
14 RFi 13
T0 16 PRESCALER 15 BIT COUNTER PHASE COMPAR.
5I
CHARGE PUMP
16 VD
1 PD OSC 512
12 15 Vs GND
2 3 CRYSTAL
95 10730
Figure 1. Block diagram
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Rev. A1: 25.10.1995
TELEFUNKEN Semiconductors
U6225B
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol PD Q1 Q2 SDA SCL SW7 SW6 SW5 SW4 AS / ENA SW1 / Lock Vs RFi RFi GND VD Function Charge pump output Crystal Crystal Data in/output Clock input Switching output open collector Switching output open collector Switching output open collector Switching output open collector Address select / enable input Switching / lock output open collector Supply voltage RF input RF input Ground Active filter output
Pin Description
PD Q1 Q2 SDA SCL SW7 SW6 SW5 1 2 3 4 5 6 7 8 16 VD 15 GND 14 RFi 13 RFi 12 VS 11 SW1/ Lock 10 AS/ ENA 9 SW4
95 10729
Figure 2.
Absolute Maximum Ratings
All voltages are referred to GND (Pin 15) Parameters Supply voltage RF input voltage Switching output current Pin 6 - 9, 11 Total current of switching outputs Switching output voltage in off state: in on state: Bus input/output voltage Pin 12 Pin 13, 14 Open collectors Open collectors Pin 6 - 9, 11 Pin 6 - 9, 11 Symbol Vs RFi SW 1, 4-7 SW 1, 4-7 SW 1, 4-7 Value -0.3 to 6 -0.3 to Vs+0.3 -1 to 15 50 -0.3 to 14 -0.3 to 6 -0.3 to 6 -0.3 to 6 -1 to 5 -0.3 to Vs+0.3 -0.3 to Vs+0.3 -0.3 to Vs+0.3 -0.3 to Vs+0.3 -40 to 125 -40 to 125 Unit V V mA mA V V V V mA V V V V C C
Pin 4 Pin 5 SDA output current open collector Pin 4 Address select voltage Pin 10 Charge pump output voltage Pin 1 Active filter output voltage Pin 16 Crystal oscillator voltage Pin 2 Junction temperature Storage temperature
VSDA VSCL ISDA VAS / ENA PD VD Q1 Tj Tstg
Rev. A1: 25.10.1995
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U6225B
Operating Range
All voltages are referred to GND (Pin 15) Supply voltage Ambient temperature Input frequency Progr. divider Parameters Pin 12 Pin 13, 14 Symbol Vs Tamb RFi SF
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Min. 4.5 0 250 256
Typ.
Max. 5.5 70 2900 32767
Unit V C MHz
Thermal Resistance
Parameters Junction ambient Symbol RthJA Value 110 Unit K/W
Electrical Characteristics
Test conditions: VS = 5 V, Tamb = 25C, unless otherwise specified Parameters Supply current Input sensitivity Input frequency Test Conditions / Pins SW 1, 4, 5, 6, 7 = 0 Pin 12 fi = 250 MHz, Pin 13 fi = 750-2900 MHz, Pin 13 Symbol Is Vi 1) Vi 1) Min. 18 100 20 Typ. 23 Max. 28 300 300 Unit mA mVrms mVrms
Crystal oscillator Recommended crystal series resistance Crystal oscillator drive Pin 2 level Crystal oscillator source Nominal spread 15% impedance Pin 2 External reference input AC coupled sinewave frequency Pin 2 External reference input AC coupled sinewave amplitude Pin 2 Switching outputs (SW4-7,1), lock output, open collector Pin 6-9, 11 Leakage current VH = 13.5 V IL Saturation voltage IL = 10 mA VSL 2) Charge pump output (PD) Charge pump current `H' 5I = H, VPD = 2V IPDH Pin 1 Charge pump current `L' 5I = L, VPD = 2V IPDL Pin 1 Charge pump leakage T0 = 0, VPD = 2V IPDTRI current Pin 1 Charge pump amplifier Pin 1, 16 gain Bus inputs (SDA, SCL) Input voltage Pin 4, 5 Vi `H' Pin 4, 5 Vi `L' 4 (12)
10 50 -650 2 70
200
W
mVrms
W
8 200 10 0.5 MHz mVrms
mA
V
180 50 5 6400 3 5.5 1.5
mA mA
nA
V V
Rev. A1: 25.10.1995
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Test Conditions / Pins Symbol VSCL `H' = Vs Pin 4, 5 li 'H' VSCL `L' = 0 V Pin 4, 5 li 'L' Leakage current Vs = 0 V Pin 4, 5 IL Output voltage SDA (open ISDA `L' = 2 mA, Pin 4 VSDA 'L' collector) Address selection / Enable input (AS, ENA) Input current VAS `H' = Vs Pin 10 liAS 'H' VAS `L' = 0 Pin 10 liAS 'L' 1) 2) Parameters Input current Min. -10 Typ.
U6225B
Max. 10 10 0.4 Unit
mA mA mA
V
10 -100
mA mA
RMS-voltage calculated from the measured available power on 50 W Tested with one switch active, the collector voltage may not exceed 6 V frefosc: Reference oscillator frequency: 3.2 / 4 MHz crystal or external reference frequency
Description
The U6225B-B is a single chip PLL designed for SAT-TV receiver systems. It consists of a divide-by-16 prescaler with an integrated preamplifier, a 15 bit programmable divider, a crystal oscillator with a divide-by-512 reference divider, a phase/frequency detector together with a charge-pump, which is driving the tuning amplifier. Only one external transistor is required for varactor line driving. The device can be controlled via I2C-bus format or the 3-wire-bus format. It detects automatically which bus format is received, therefore there is no need of a bus selection pin. In I2C-bus mode the device has 4 programmable addresses, programmed by applying a specific input voltage to the address select input, enabling the use of up to four synthesizers in a system. The same pin serves in 3-wire-bus mode as the enable signal input. Five open collector outputs for switching functions are included, which are capable of sinking at least 10 mA. One of these open collector outputs serves as Locksignal output in the 3-wire-bus mode.
Functional Description
The U6225B-B is programmed via 2-wire I2C bus or 3-wire bus depending on the received data format. The three bus inputs pin 4, 5, 10 are used as SDA, SCL and ADDRESS SELECT inputs in I2C-bus mode and as DATA, CLOCK and ENABLE inputs in 3-wire bus mode. The data includes the scaling factor SF (15 bit) and switching output information. In I2C-bus mode there are some additional functions for testing of the device included.
The input amplifier together with a divide-by-16 prescaler gives an excellent sensitivity (see `Typical Prescaler Input Sensitivity'). The input impedance is shown in the diagram `Typical Input Impedance'. When a new divider ratio according to the requested fvco is entered, the phase detector and charge pump together with the tuning amplifier adjusts the control voltage of the VCO until the output signals of the programmable divider and the reference divider are in frequency and phase locked. The reference frequency may be provided by an external source capacitively coupled into pin 2, or by using an on-board crystal with an 18 pF capacitor in series. The crystal operates in the series resonance mode. The reference divider division ratio is fixed to 512. Therefore with a 4 MHz crystal the comparison frequency is 7.8125 kHz, which gives 125 kHz steps for the VCO, or with a 3.2 MHz crystal respectively 6.25 kHz comparison frequency and 100 kHz VCO step size. In addition there are switching outputs available for bandswitching and other purposes.
Application
A typical application is shown on page ?. All input / output interface circuits are shown on page ?. Some special features which are related to test- and alignment procedures for tuner production are explained together within the following bus mode description.
I2C-Bus Description
When the U6225B-B is controlled via 2-wire I2C-bus format, then data and clock signals are fed into the SDA and SCL lines respectively. The table 'I2C-BUS DATA FORMAT' describes the format of the data and shows how to select the device address by applying a voltage at pin 10. When the correct address byte is received, the SDA line is pulled low by the device during the acknowledge pe-
Oscillator Frequency Calculation
fvco = 16 * SF * frefosc / 512 fvco: Locked frequency of voltage controlled oscillator SF: Scaling factor of programmable 15-bit-divider Rev. A1: 25.10.1995
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U6225B
riod, and then also during the acknowledge periods, when additional data bytes are programmed. After the address transmission (first byte), data bytes can be sent to the device. There are four data bytes requested to fully program the device. The table `I2C-Bus Pulse Diagram' shows some possible data transfer examples. Programmable divider bytes PDB1 and PDB2 are stored in a 15 bit latch and are controlling the division ratio of the 15 bit programmable divider. The control Byte CB1 allows to control the following special functions: to logic 1
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D T0-bit allows to disable the charge pump when it is set D OS-bit disable the charge pump drive amplifier output
when it is set to logic 1. Only in I2C bus mode the charge pump current can be controlled. In 3-wire-bus mode there is always the high charge pump current active. The OS-bit function disables the complete PLL function. This allows the tuner alignment by suppling the tuning voltage directly through the 30 V supply voltage of the tuner. The control byte CB2 programs the switching outputs SW 1, 4, 5, 6, 7; a logic 0 for high impedance output (off) and a logic 1 for low impedance output (on).
D 5I-bit switches between low and high charge pump
current
D T1-bit enables divider test mode when it is set to
logic 1
Description Address byte Progr. divider byte 1 Progr. divider byte 2 Control byte 1 Control byte 2 MSB 1 0 n7 1 SW7 1 n14 n6 5I SW6 0 n13 n5 T1 SW5
I2C Bus Data Format 0 n12 n4 T0 SW4 0 n11 n3 X X AS1 n10 n2 X X AS2 n9 n1 X SW1 LSB 0 n8 n0 OS X A A A A A
A = Acknowledge; X = not used; Unused bits of controlbyte 2 should be 0 for lowest power consumption n0 ... n14 T0, T1 Scaling factor (SF) Testmode selection SF = 16384*n14+8192*n13+ ... +2*n1 + n0 T1 = 1: divider test mode on T1 = 0: divider test mode off T0 = 1: charge pump disable T0 = 0: charge pump enable SW1, SW4, SW5, SW6, SW7 = 1: open collector active 5I = 1: high current 5I = 0: low current OS = 1: varicap driver disable OS = 0: varicap drive enable
SW1, 4, 5, 6, 7 5I OS AS1, AS2
Switching outputs Charge pump current switch Output switch Address selection pin 10
AS1 0 0 1 1
AS2 1 0 0 1
Address 1 2 3 4
Dec. Value 194 192 196 198
Voltage at pin 10 open 0 to 10% Vs 40 to 60% Vs 90 to 100% Vs
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Rev. A1: 25.10.1995
TELEFUNKEN Semiconductors
U6225B
/ A / 1.BYTE /A/ 2.BYTE /A/ 3.BYTE /A/ 4.BYTE /A/
I2C-Bus Pulse Diagram
ADDRESS BYTE
SDA
SCL START 1 2 3 4 5 6 7 8 9 1... 8 9 1... 8 9 1... 8 9 1... 8 9 STOP
95 10731
Figure 3.
Data transfer examples START ADR PDB1 PDB2 CB1 CB2 STOP START ADR CB1 CB2 PDB1 PDB2 STOP START ADR PDB1 PDB2 CB1 STOP START ADR CB1 CB2 PDB1 STOP START ADR PDB1 PDB2 STOP START ADR CB1 CB2 STOP START ADR CB1 STOP
Description START = Start condition ADR = Address byte PDB1 = Progr. divider byte 1 PDB2 = Prgr. divider byte 2 CB1 = Control byte 1 CB2 = Control byte 2 STOP = Stop condition
I2C-Bus Timing
t
W STT 95 10732
SDA
t S STT
SCL
t LOW
t HIGH
tR
tF
t S STP
t H STT
START CLOCK
t S DAT
t H DAT
STOP
DATACHANGE
Figure 4.
Parameters Rise time SDA, SCL Fall time SDA, SCL Clock frequency SCL Clock `H' pulse Clock `L' pulse Hold time start Waiting time start Set-up time start Set-up time stop Set-up time data Hold time data
Symbol tR tF fSCL tHIGH tLOW tH STT tW STT tS STT tS STP tS DAT tH DAT
Min.
Typ.
0 4 4 4 4 4 4 0.3 0
Max. 15 15 100
Unit
ms ms
kHz
ms ms ms ms ms ms ms ms
Rev. A1: 25.10.1995
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U6225B
3-Wire-Bus Description
When the U6225B-B is controlled via 3-wire bus format, then DATA, CLOCK and ENABLE signals are fed into the SDA, SCL and AS/ENA lines respectively. The diagram '3-WIRE-BUS PULSE DIAGRAM' shows the data format. The data consist of a single word, which contains the programmable divider and switch information. Only during the enable high period the data is clocked into the internal data shift register on the negative clock transition. During enable low periods the clock input is disabled. New data words are only accepted by the internal data latches from the shift register on a negative transition of the enable signal when during the high period of the enable exactly nineteen clock pulses were send. The data sequence and the timing is described in the following diagrams.
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In 3-wire-bus mode pin 11 becomes automatically the Locksignal output. An improved lock detect circuit generates a flag when the loop has attained lock. 'In lock' is indicated by a low impedance state (on) of the open collector output. In 3-wire-bus mode there is always the high charge pump current active. Only in I2C-bus mode the charge pump current can be controlled. The complete PLL function can be disabled by programming a normally not used division ratio of zero. This allows the tuner alignment by supplying the tuning voltage directly through the 30 V supply voltage of the tuner.
3-Wire-Bus Pulse Diagram
P7 SDA 4 Bit Ports P6 P5 15 Bit scaling factor SF P4 MSB LSB
SCL
AS / ENA
95 10733
Figure 5.
3-Wire-Bus Timing
Data LSB
Clock
Enable
TL
TS
TC
TH
TSL
TT
95 10734
Figure 6.
Parameters Set up time Enable hold time Clock width Enable set up time Enable between two transmissions Data hold time
Symbol TS TSL TC TL TT TH
Min. 2 2 2 10 10 2
Typ.
Unit
ms ms ms ms ms ms
Rev. A1: 25.10.1995
8 (12)
TELEFUNKEN Semiconductors
U6225B
Vs
Input/Output Interface Circuits
Vref
1.5K RF1 RF2
1.5K
Port
95 10735
95 10738
Figure 7. RF input
Figure 10. Ports
Vs
Vs
1K
Crystal Q1
AS/ENA
Crystal Q2
95 10736 95 10739
Figure 8. Reference oscillator
Figure 11. Address select/ Enable input
Vs
Vs
60
2K PD
SDA/SCL SDA only ACK OS (O/P Disable)
95 10737 95 10740
VD 45K
Figure 9. SCL and SDA input Figure 12. Loop amplifier
Rev. A1: 25.10.1995
9 (12)
U6225B
Typical Prescaler Input Sensitivity
Vi (mV RMS on 50 Ohm) 1000
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100
OPERATING WINDOW
10
1 0 500 1000 1500 2000 2500 Frequency (MHz) 3000 3500 4000
95 10741
Figure 13.
Typical Input Impedance
j
0.5j
2j
0.2j 4.0 GHz 3.5 GHz 0
5j
-0.2j
95 9927
10 (12)
AAA AAA AAA AAA AA AA A AA AA AA AA A AA AA
0.2 0.5 1 2 5 3.0 GHz 100 MHz 2.5 GHz -5j 500 MHz 2.0 GHz 1 GHz -0.5j -2j Z0 = 50 W -j
1
Figure 14.
AAA
Rev. A1: 25.10.1995
TELEFUNKEN Semiconductors
U6225B
Application Circuit
TUNER fTV f IF f VCO
30 V 22 k 22 n 4 MHz
3 1 2
18 p
1n
13
RFi
14
1n
12 15
Vs GND AS / ENA SCL SDA from uC
39 k 12 V
100 n
16
10 5 6 7 8 SW4 9 11 SW1 / Lock 4
22 k 10 k 22 k 10 k 22 k 10 k
SW7 SW6 SW5
95 10742
Figure 15.
Dimensions in mm
Package: SO-16 small
94 8875
Rev. A1: 25.10.1995
11 (12)
U6225B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to
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1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423
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Rev. A1: 25.10.1995

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